混合層程式

`define INCREMENT 6'b100100
`define PASSB 6'b101010

`define NUM_STATE_BITS 1
`define IDLE 1'b0
`define COMPUTE 1'b1

module slow_div_ctrl(pb,ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,sysclk);
input pb,r2gey,sysclk;
output ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3;

reg [`NUM_STATE_BITS-1:0] present_state;
wire pb;
reg ready;
reg [5:0] aluctrl;
reg ldr1,ldr2,clrr2,incr2,ldr3;
wire r2gey,sysclk;
always
begin
@(posedge sysclk) enter_new_state(`IDLE);
//r1 <= @(posedge sysclk) 0;
//r2 <= @(posedge sysclk) y;
ready = 1;
ldr1 = 1;
clrr2 = 0;
ldr2=1;
aluctrl = 6'b001110;
if (pb)
begin
while (r2gey>=1 pb)
begin
@(posedge sysclk) enter_new_state(`COMPUTE);
ready = 0;
//r1 <= @(posedge sysclk) r1 + x;
//r2 <= @(posedge sysclk) r2 - 1;
//r3 <= @(posedge sysclk) r1;
aluctrl = `INCREMENT;
ldr1 = 1;
ldr2 = 0;
clrr2=0;
incr2 = 1;
ldr3 = 1;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1{ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3}=0;
end
endtaskendmodule



module slow_div_arch(aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,x,y,r3bus,sysclk);
input aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,x,y,sysclk;
output r2gey,r3bus;
wire [5:0] aluctrl;
wire ldr1,ldr2,clrr2,incr2,ldr3,r2gey,sysclk;
wire [11:0] x,y,r3bus;
wire [11:0] alubus,r1bus,r2bus;

enabled_register #12 r1(alubus,r1bus,ldr1,sysclk);
alu181 #12 alu(r1bus,x,aluctrl[5:2],aluctrl[1],aluctrl[0],,alubus,);
comparator #12 cmp(r2lty,,,r2bus,1'b1);
not inv(r2gey,r2lty);

counter_register #12 r2(y,r2bus,,ldr2,incr2,clrr2,sysclk);
enabled_register #12 r3(r1bus,r3bus,ldr3,sysclk);

always @(posedge sysclk) #20
begin
$display("%d r1=%d r2=%d r3=%d pb=%b ready=%b", $time, r1bus,r2bus,r3bus,slow_div_machine.pb,slow_div_machine.ready);
$display("ldr2=%b,incr2=%b,clrr2=%b y=%d ",ldr2,incr2,clrr2,y); $write( " %b %b %b",ldr1,{ldr2,clrr2,incr2},ldr3);
$display(" alubus=%d x=%d r2gey=%b",alubus,x,r2gey);
$display("\n=============================");
$display( " aluctrl=%b",aluctrl);
end
endmodule
module slow_div_system(pb,ready,x,y,r3,sysclk);
input pb,x,y,sysclk;
output ready,r3;
wire pb;
wire [11:0] x,y;
wire ready;
wire [11:0] r3;
wire sysclk;

wire [5:0] aluctrl;
wire ldr1,ldr2,clrr2,incr2,ldr3,r2gey;

slow_div_arch a(aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,x,y,r3,sysclk);
slow_div_ctrl c(pb,ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,sysclk);
endmodule
module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 8;
y = 7;
#250;
@(posedge sysclk);
begin
@(posedge sysclk);
pb = 1;
//wait(~ready);
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x*y === quotient)
$display("ok");
else
$display("error x=%d y=%d x*y=%d quotient=%d",x,y,x*y,quotient);
end
$stop;
endendmodule