結構模式結果

結構模式程式

always
@(present_state or r2gey or pb)
begin
next_state = present_state&r2geypb;
ldr1 = 1;
ldr2= ~present_state;
ldr3= present_state;
clrr2 = 0;
incr2 = present_state;
aluctrl[5] = present_state;
aluctrl[4] = 0;
aluctrl[3] = ~present_state;
aluctrl[2] = 1;
aluctrl[1] = ~present_state;
aluctrl[0] = 0;
ready = ~present_state;
end
endmodule

畫成卡諾圖

結構化對應表

執行混合層訊號結果

混合層執行結果

混合層架構程式

// file: archdev.v//
date: 4/26/93
//
// Copyright 1993 Mark Arnold
// All rights reserved
//
// include file with modules that simulate devices
// which are the basic architectural building blocks
// used in COSC 4700
//


// This models a synchronous enabled register
// The contents are unchanged unless the enable signal is true
// Examples: 74LS377, 74LS378
module enabled_register(di,do,enable,clk);
parameter SIZE = 1,
DELAY = 0,
SETUP = 0;
input di,enable,clk;
output do;
reg [SIZE-1:0] do;
wire [SIZE-1:0] di;
reg [SIZE-1:0] internal_do;
wire enable;
wire clk;
integer last_change;
integer t_setup, t_clk_to_out; //to allow interactive experiment

initial
begin
last_change = 0;
t_setup = SETUP;
t_clk_to_out = DELAY;
end

always @(posedge clk)
begin
if (enable)
begin
do = 'oxxxx;
internal_do = di;
if ($time-last_change > t_setup)
begin
if (t_clk_to_out>0)
#t_clk_to_out do = internal_do;
else
do = internal_do;
end
else
$display("setup violation, time=",$time);
end
end

always @(enable or di)
begin
if (($time % 100) != 0)
last_change = $time;
endendmodule


// This models a synchronous binary counter register
// The contents are unchanged unless count, load or clr is
// true at the rising edge:
//
// clr load count action
// 1 - - do becomes 0
// 0 1 - do becomes di
// 0 0 1 do becomes do - 1
// 0 0 0 do unchanged
//
// Example: 74LS163


module counter_register(di,do,tc,load,count,clr,clk);
parameter SIZE = 1,
DELAY = 0,
SETUP = 0;
input di,load,count,clr,clk;
output do,tc;
reg [SIZE-1:0] do;
wire [SIZE-1:0] di;
reg [SIZE-1:0] internal_do;
reg tc;
wire load,count,clr;
wire clk;
integer last_change;
integer t_setup, t_clk_to_out;
//to allow interactive experiment

initial
begin
last_change = 0;
t_setup = SETUP;
t_clk_to_out = DELAY;
end

always @(posedge clk)
begin
if (clr load count)
begin
if (clr)
internal_do = 0;
else
begin
if (load)
internal_do = di;
else
begin
if (count)
internal_do = do-1;
end
end
do = 'bx;
tc = 'bx;
if (($time-last_change > t_setup))
begin
if (t_clk_to_out>0)
#t_clk_to_out do = internal_do;
else
do = internal_do;
end
else
$display("setup violation, time=",$time);
tc = 0+do===(1 << SIZE) - 1;
end
end

always @(clr or load or count or di)
begin
if (($time % 100) != 0)
last_change = $time;
end
endmodule


// This models is a purely combinational ALU
// It is a universal logic unit on each bit of b,a when m=1
// It does 16 somewhat arbitrary arithmetic operations when m=0

module alu181(a,b,s,m,cin,cout,f,zero);
parameter SIZE = 1, DELAY = 0;
input a,b,s,m,cin;
output cout,f,zero;
wire [SIZE-1:0] a,b;
wire m,cin;
wire [3:0] s;
reg [SIZE-1:0] f;
reg cout,zero;
integer t;
integer i;
event change;
initial t = DELAY;

always @(a or b or s or m or cin)
start_change;

always @change
begin : change_block
if (t != 0)
#t;
if (m)
cout = 0; //not sure
case ({m,s})
5'b00000: {cout,f} = a + cin;
5'b00001: {cout,f} = (a b) + cin;
5'b00010: {cout,f} = (a (~b)) + cin;
5'b00011: {cout,f} = (1 << SIZE) - 1 + cin;
5'b00100: {cout,f} = a + (a&(~b)) + cin;
5'b00101: {cout,f} = (ab) + (a&(~b)) + cin;
5'b00110: {cout,f} = a - b - 1 + cin;
5'b00111: {cout,f} = (a&(~b)) - 1 + cin;
5'b01000: {cout,f} = a + (a&b) + cin;
5'b01001: {cout,f} = a + b + cin;
5'b01010: {cout,f} = (a(~b)) + (a&b) + cin;
5'b01011: {cout,f} = (a&b) - 1 + cin;
5'b01100: {cout,f} = a + a + cin;
5'b01101: {cout,f} = (a(~b)) + a + cin;
5'b01110: {cout,f} = (ab) + a + cin;
5'b01111: {cout,f} = a - 1 + cin;
5'b10000: f = ~a;
5'b10001: f = ~(ab);
5'b10010: f = (~a)&b;
5'b10011: f = 0;
5'b10100: f = ~(a&b);
5'b10101: f = ~b;
5'b10110: f = a^b;
5'b10111: f = a&(~b);
5'b11000: f = (~a)b;
5'b11001: f = ~(a^b);
5'b11010: f = b;
5'b11011: f = a&b;
5'b11100: f = (1 << SIZE) - 1 + cin;
5'b11101: f = a(~b);
5'b11110: f = ab;
5'b11111: f = a;
default: f = 'bx;
endcase
zero = f == 0;
end
task start_change;
begin
if (t != 0)
begin
f = 'bx;
disable change_block;
#0;
end
-> change;
end
endtaskendmodule


// This model is two input comparator
// Example: 74LS85

module comparator(a_lt_b, a_eq_b, a_gt_b, a, b);
parameter SIZE = 1, DELAY = 0;
output a_lt_b, a_eq_b, a_gt_b;
input a, b;
wire [SIZE-1:0] a,b;
reg a_lt_b, a_eq_b, a_gt_b;
integer t;
event change;

initial
t = DELAY;

always @(a or b)
start_change;

always @change
begin : change_block
if (t != 0)
#t;
a_eq_b = a == b;
a_lt_b = a < b;
a_gt_b = a > b;
end

task start_change;
begin
if (t != 0)
begin
a_eq_b = 'bx;
a_lt_b = 'bx;
a_gt_b = 'bx;
disable change_block;
#0;
end
-> change;
end
endtask
endmodule

混合層程式

`define INCREMENT 6'b100100
`define PASSB 6'b101010

`define NUM_STATE_BITS 1
`define IDLE 1'b0
`define COMPUTE 1'b1

module slow_div_ctrl(pb,ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,sysclk);
input pb,r2gey,sysclk;
output ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3;

reg [`NUM_STATE_BITS-1:0] present_state;
wire pb;
reg ready;
reg [5:0] aluctrl;
reg ldr1,ldr2,clrr2,incr2,ldr3;
wire r2gey,sysclk;
always
begin
@(posedge sysclk) enter_new_state(`IDLE);
//r1 <= @(posedge sysclk) 0;
//r2 <= @(posedge sysclk) y;
ready = 1;
ldr1 = 1;
clrr2 = 0;
ldr2=1;
aluctrl = 6'b001110;
if (pb)
begin
while (r2gey>=1 pb)
begin
@(posedge sysclk) enter_new_state(`COMPUTE);
ready = 0;
//r1 <= @(posedge sysclk) r1 + x;
//r2 <= @(posedge sysclk) r2 - 1;
//r3 <= @(posedge sysclk) r1;
aluctrl = `INCREMENT;
ldr1 = 1;
ldr2 = 0;
clrr2=0;
incr2 = 1;
ldr3 = 1;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1{ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3}=0;
end
endtaskendmodule



module slow_div_arch(aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,x,y,r3bus,sysclk);
input aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,x,y,sysclk;
output r2gey,r3bus;
wire [5:0] aluctrl;
wire ldr1,ldr2,clrr2,incr2,ldr3,r2gey,sysclk;
wire [11:0] x,y,r3bus;
wire [11:0] alubus,r1bus,r2bus;

enabled_register #12 r1(alubus,r1bus,ldr1,sysclk);
alu181 #12 alu(r1bus,x,aluctrl[5:2],aluctrl[1],aluctrl[0],,alubus,);
comparator #12 cmp(r2lty,,,r2bus,1'b1);
not inv(r2gey,r2lty);

counter_register #12 r2(y,r2bus,,ldr2,incr2,clrr2,sysclk);
enabled_register #12 r3(r1bus,r3bus,ldr3,sysclk);

always @(posedge sysclk) #20
begin
$display("%d r1=%d r2=%d r3=%d pb=%b ready=%b", $time, r1bus,r2bus,r3bus,slow_div_machine.pb,slow_div_machine.ready);
$display("ldr2=%b,incr2=%b,clrr2=%b y=%d ",ldr2,incr2,clrr2,y); $write( " %b %b %b",ldr1,{ldr2,clrr2,incr2},ldr3);
$display(" alubus=%d x=%d r2gey=%b",alubus,x,r2gey);
$display("\n=============================");
$display( " aluctrl=%b",aluctrl);
end
endmodule
module slow_div_system(pb,ready,x,y,r3,sysclk);
input pb,x,y,sysclk;
output ready,r3;
wire pb;
wire [11:0] x,y;
wire ready;
wire [11:0] r3;
wire sysclk;

wire [5:0] aluctrl;
wire ldr1,ldr2,clrr2,incr2,ldr3,r2gey;

slow_div_arch a(aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,x,y,r3,sysclk);
slow_div_ctrl c(pb,ready,aluctrl,ldr1,ldr2,clrr2,incr2,ldr3,r2gey,sysclk);
endmodule
module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 8;
y = 7;
#250;
@(posedge sysclk);
begin
@(posedge sysclk);
pb = 1;
//wait(~ready);
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x*y === quotient)
$display("ok");
else
$display("error x=%d y=%d x*y=%d quotient=%d",x,y,x*y,quotient);
end
$stop;
endendmodule

混合層ASM圖

混合層架構圖

乘法機行為層-END

乘法機行為層-修改程式2

`define NUM_STATE_BITS 1

`define IDLE 1'b0

`define COMPUTE 1'b1

module slow_div_system(pb,ready,x,y,r3,sysclk);

input pb,x,y,sysclk;

output ready,r3;

wire pb;

wire [11:0] x,y;

reg ready;

reg [11:0] r1,r2,r3;

reg [`NUM_STATE_BITS-1:0] present_state;

always

begin

@(posedge sysclk) enter_new_state(`IDLE);

r1 <= @(posedge sysclk) 0;

r2 <= @(posedge sysclk) y;

r3 <= @(posedge sysclk) 0;

ready = 1;

if (pb)

begin

while (r2 >= 1 │ pb)

begin

@(posedge sysclk) enter_new_state(`COMPUTE);

r1 <= @(posedge sysclk) r1 + x;

r2 <= @(posedge sysclk) r2 - 1;

r3 <= @(posedge sysclk) r1;

end

end

end

task enter_new_state;

input [`NUM_STATE_BITS-1:0] this_state;

begin

present_state = this_state;

#1 ready=0;

end

endtask

always @(posedge sysclk) #20

$display("%d r1=%d r2=%d r3=%d pb=%b ready=%b", $time, r1,r2,r3, pb, ready);

endmodule

module top;

reg pb;

reg [11:0] x,y;

wire [11:0] quotient;

wire ready;

integer s;

wire sysclk;

cl #20000 clock(sysclk);

slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial

begin

pb= 0;

x = 8;

y = 7;

#250;

@(posedge sysclk);

begin

@(posedge sysclk);

pb = 1;

@(posedge sysclk);

pb = 0;

@(posedge sysclk);

wait(ready);

@(posedge sysclk);

if (x*y === quotient)

$display("ok");

else

$display("error x=%d y=%d x*y=%d quotient=%d",x,y,x*y,quotient);

end

$stop;

end

endmodule

乘法機行為層-修改程式

乘法機行為層

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