乘法機行為層-END

乘法機行為層-修改程式2

`define NUM_STATE_BITS 1

`define IDLE 1'b0

`define COMPUTE 1'b1

module slow_div_system(pb,ready,x,y,r3,sysclk);

input pb,x,y,sysclk;

output ready,r3;

wire pb;

wire [11:0] x,y;

reg ready;

reg [11:0] r1,r2,r3;

reg [`NUM_STATE_BITS-1:0] present_state;

always

begin

@(posedge sysclk) enter_new_state(`IDLE);

r1 <= @(posedge sysclk) 0;

r2 <= @(posedge sysclk) y;

r3 <= @(posedge sysclk) 0;

ready = 1;

if (pb)

begin

while (r2 >= 1 │ pb)

begin

@(posedge sysclk) enter_new_state(`COMPUTE);

r1 <= @(posedge sysclk) r1 + x;

r2 <= @(posedge sysclk) r2 - 1;

r3 <= @(posedge sysclk) r1;

end

end

end

task enter_new_state;

input [`NUM_STATE_BITS-1:0] this_state;

begin

present_state = this_state;

#1 ready=0;

end

endtask

always @(posedge sysclk) #20

$display("%d r1=%d r2=%d r3=%d pb=%b ready=%b", $time, r1,r2,r3, pb, ready);

endmodule

module top;

reg pb;

reg [11:0] x,y;

wire [11:0] quotient;

wire ready;

integer s;

wire sysclk;

cl #20000 clock(sysclk);

slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial

begin

pb= 0;

x = 8;

y = 7;

#250;

@(posedge sysclk);

begin

@(posedge sysclk);

pb = 1;

@(posedge sysclk);

pb = 0;

@(posedge sysclk);

wait(ready);

@(posedge sysclk);

if (x*y === quotient)

$display("ok");

else

$display("error x=%d y=%d x*y=%d quotient=%d",x,y,x*y,quotient);

end

$stop;

end

endmodule

乘法機行為層-修改程式

乘法機行為層